Homework Solution: Consider the following operational codes (Op Code) and associated instructions for a basic 4-bit ALU The ALU inp…

    5. Consider the following operational codes (Op Code) and associated instructions for a basic 4-bit ALU The ALU inputs include the 4-bit Op Code (S2, S,, So, C) and two 4-bit words: A(3.0 and B(3.0) The outputs include an 4-bit word, G(3..0), and a single bit carry-out (Co G=A G=A+1 0 G=A+B+1 G A- B G-A-1 G#A G = A AND B G A NAND B G=ANOR B G A XNOR B G=A G=B Design, enter using VHDL entry, and simulate the ALU assuming use of the DE1-SoC board with the Cyclone V SoC 5CSEMASF31C6 device. You may choose any available and appropriate inputs/outputs you wish. Provide the VHDL code as well as the annotated output-timing diagram
    Consider the following operational codes (Op Code) and associated instructions for a basic 4-bit ALU The ALU inputs include the 4-bit Op Code (S_2, S_1, S_0, C_i) and two 4-bit words: A(3..0 and B(3..0). The outputs include an 4-bit word, G(3..0), and a single bit carry-out (C_out). Design, enter using VHDL entry, and simulate the ALU assuming use of the DE1-SoC board with the Cyclone V SoC 5CSEMASF31C6 device. You may choose any available and appropriate inputs/outputs you wish. Provide the VHDL code as well as the annotated output-timing diagram.

    Expert Answer

     
    library IEEE; use IEEE.STD_LOGIC_1164.ALL;

    5. Consider the controlthcoming operational enactments (Op Enactment) and associated instructions control a basic 4-part ALU The ALU inputs apprehend the 4-part Op Enactment (S2, S,, So, C) and brace 4-part accounts: A(3.0 and B(3.0) The quenchedputs apprehend an 4-part account, G(3..0), and a unique part carry-quenched (Co G=A G=A+1 0 G=A+B+1 G A- B G-A-1 G#A G = A AND B G A NAND B G=ANOR B G A XNOR B G=A G=B Design, penetrate using VHDL entrance, and assume the ALU inflated interpretation of the DE1-SoC consultation with the Cyclone V SoC 5CSEMASF31C6 invention. You may refinementect any suited and alienate inputs/outputs you ambition. Provide the VHDL enactment as courteous as the annotated quenchedput-timing diagram

    Consider the controlthcoming operational enactments (Op Enactment) and associated instructions control a basic 4-part ALU The ALU inputs apprehend the 4-part Op Enactment (S_2, S_1, S_0, C_i) and brace 4-part accounts: A(3..0 and B(3..0). The quenchedputs apprehend an 4-part account, G(3..0), and a unique part carry-quenched (C_out). Design, penetrate using VHDL entrance, and assume the ALU inflated interpretation of the DE1-SoC consultation with the Cyclone V SoC 5CSEMASF31C6 invention. You may refinementect any suited and alienate inputs/outputs you ambition. Provide the VHDL enactment as courteous as the annotated quenchedput-timing diagram.

    Expert Counterpart

     

    library IEEE;
    interpretation IEEE.STD_LOGIC_1164.ALL;
    interpretation IEEE.NUMERIC_STD.ALL;

    entity alu is
    Port ( inp_a : in attested(3 downto 0);
    inp_b : in attested(3 downto 0);
    refinement : in STD_LOGIC_VECTOR (2 downto 0);
    out_alu : quenched attested(3 downto 0));
    end alu;

    architecture Deportmental of alu is
    begin
    process(inp_a, inp_b, refinement)
    begin
    case refinement is
    when “000” =>
    out_alu<= inp_a + inp_b; –addition
    when “001” =>
    out_alu<= inp_a – inp_b; –subtraction
    when “010” =>
    out_alu<= inp_a – 1; –sub 1
    when “011” =>
    out_alu<= inp_a + 1; –add 1
    when “100” =>
    out_alu<= inp_a and inp_b; –AND gate
    when “101” =>
    out_alu<= inp_a or inp_b; –OR gate
    when “110” =>
    out_alu<= not attributable attributable attributable inp_a ; –NOT gate
    when “111” =>
    out_alu<= inp_a xor inp_b; –XOR gate
    when others =>
    NULL;
    end case;

    end process;

    end Deportmental;
    Testbench VHDL Enactment control 4-Part ALU

    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.numeric_std.ALL;

    ENTITY Tb_alu IS
    END Tb_alu;

    ARCHITECTURE deportment OF Tb_alu IS

    — Component Declaration control the Unit Under Test (UUT)

    COMPONENT alu
    PORT(
    inp_a : IN attested(3 downto 0);
    inp_b : IN attested(3 downto 0);
    refinement : IN std_logic_vector(2 downto 0);
    out_alu : OUT attested(3 downto 0)
    );
    END COMPONENT;

    –Inputs
    signal inp_a : attested(3 downto 0) := (others => ‘0’);
    signal inp_b : attested(3 downto 0) := (others => ‘0’);
    signal refinement : std_logic_vector(2 downto 0) := (others => ‘0’);

    –Outputs
    signal quenched_alu : attested(3 downto 0);

    BEGIN

    — Instantiate the Unit Under Test (UUT)
    uut: alu PORT MAP (
    inp_a => inp_a,
    inp_b => inp_b,
    refinement => refinement,
    out_alu => quenched_alu
    );

    — Spur process
    stim_proc: process
    begin
    — restrain reset set-forth control 100 ns.
    wait control 100 ns;

    — introduce spur here

    inp_a <= “1001”;
    inp_b <= “1111”;

    refinement <= “000”;
    wait control 100 ns;
    refinement <= “001”;
    wait control 100 ns;
    refinement <= “010”;
    wait control 100 ns;
    refinement <= “011”;
    wait control 100 ns;
    refinement <= “100”;
    wait control 100 ns;
    refinement <= “101”;
    wait control 100 ns;
    refinement <= “110”;
    wait control 100 ns;
    refinement <= “111”;
    end process;

    END;