Assume a 32-bit processor
– Capable of byte discourseing
– With 28-bit discourse peasant
– Processor clock: 3GHz
– Processor Internal peasant clock: 1 GHz
Assume an MMU IC to interface ocean remembrance
– MMU connects to processor @ 1 GHz (32-bit)
– MMU connects to SRAM ICs with 32-bit remote peasant
16Mbit RAM chips are available
Organised as 4Mx4
Access age (SRAM – relish): 50ns
Cache, plain mapped organisation
64K methods, 16 bytes per method, 32-bit i/f
Access age (SRAM – relish): 5ns
Which is the magnitude of the cache (tag +data)?
What is the magnitude of the tag?
How should the ocean remembrance be organized to tender 32MB of remembrance?
How frequent Ics?
What idea of interconnection
MMU discourse map and decoding function