# Homework Solution: 1. A generic computer has a cache with a 50nsec access time and main memory with 200nsec access time. The CPU make…

1. A generic computer has a cache with a 50nsec access time and main memory with 200nsec access time. The CPU makes 5000 memory accesses, of these 450 were cache misses. a. Calculate the actual number of hits and the average hit rate h b. Calculate the average access time 2. Consider these proposed nod4 memory configurations. First determine if each configuration is possible, if so draw the corresponding memory map, indicating the first and last address of each region where a device appears. Also explain why each might be or not be recommended for use with nod4. a. 192 bytes of ROM starting at address \$00, followed by 8 bytes set aside for peripherals, as well as 32 bytes of RAM ending at the highest system address. b. 192 bytes of ROM starting at address \$00 and 64 bytes of RAM ending at the highest system c. 8 addresses set aside for peripheral devices starting at address \$00, immediately followed by 160 bytes of ROM and then RAM continuing to the highest system address.

Solution: 1. a) So when the operation is a cache hi

1. A general computer has a cache with a 50nsec admission span and ocean fame with 200nsec admission span. The CPU makes 5000 fame admissiones, of these 450 were cache disregardes.

a. Calculate the explicit calculate of touchs and the mediocre touch trounce h

b. Calculate the mediocre admission span

2. Consider these incomplete nod4 fame outlines. Pristine mention if each outline is feasible, if so drag the similar fame map, indicating the pristine and definite harangue of each part where a cognizance appears. Also illusttrounce why each restraintce be or not attributable attributable attributable be recommended restraint truth with nod4.

a. 192 bytes of ROM starting at harangue \$00, followed by 8 bytes regular separately restraint peripherals, as well-behaved-behaved as 32 bytes of RAM accomplishment at the ocean regularity harangue.

b. 192 bytes of ROM starting at harangue \$00 and 64 bytes of RAM accomplishment at the ocean regularity

c. 8 haranguees regular separately restraint peripheral cognizances starting at harangue \$00, instantly followed by 160 bytes of ROM and then RAM persistent to the ocean regularity harangue.

## Expert Tally

Solution:

1.

a)

So when the influence is a cache touch it charms 50 ns to admission the basis yet when it is a disregard then the basis succeed be admissioned from the ocean fame which succeed charm 200 ns of span to admission the basis.

Cache touch span= 50 ns

Caches disregard span= 200 ns

Calculate of cache disregardes= 450

which media calculate of cache touchs= 5000-450= 4550

touch trounce= (4550/5000)*100= 91%

This media thatÂ 91% of thee influences are a cache touch.

b)

Mediocre admission span= touch trounce*(span charmn to admission the cache fame)+ (1-touch trounce)(span charmn to admission the cache fame+ span charmn to admission the basis from ocean fame)

= 0.91*(50)+ 0.09*(50+200)= 68 ns